The present invention is a metal oxide semiconductor (MOS) large scale integrated (LSI) chip for a micro packet network interface circuit (MPAC) having an optimum chip topography, and designed to transmit and receive serial packet information in accordance with the standards specified by the International Telegraph and Telephone Consultative Committee ("CCITT") in its Recommendation X.25. In implementing Recommendation X.25, the present invention employs a novel data addressing and memory buffering scheme that substantially improves the performance of a data communications system incorporating the MPAC chip. This improvement in performance allows the central processing unit (CPU) of the host system to be used more for data processing, and less for communications control.
The MPAC chip is designed to be incorporated into electronic communications circuitry, and to implement a predefined communications protocol and provide an error-free and unambiguous exchange of information between interconnected computers and/or data terminals. The basic functions of the MPAC chip are the establishment and the termination of a logical communications connection, message integrity assurance through error detection and retransmission, the handling of special control functions such as reset and disconnect, and the formatting of information into packets to be transmitted.
In prior art implementations of Recommendation X.25, typically 4 to 6 or more semiconductor chips were required. In addition, software implementing the communications procedures (a "protocol") specified in Recommendation X.25 was required to be developed by the user. Thus, the old method required excessive printed circuit board area and costly software development.
Another problem with prior art implementations of Recommendation X.25 is that the CPU must directly attend to providing data to be transmitted, or to storing received data, on a relatively continuous basis.
The present invention overcomes the prior art problems by implementing the protocol specified in Recommendation X.25 in a single pre-programmed MOS LSI circuit. Hence, the user need not be concerned with the details of the packet switching network protocol. Furthermore, the present invention conserves printed circuit board area, and also reduces electrical power requirements.
The present invention also employs a novel indirect addressing scheme that allows the CPU to designate to the MPAC circuit, by means of "lookup" tables, areas in the system memory for storing data to be transmitted or received. Thereafter, the MPAC circuit accesses those areas by means of a direct memory accessing technique, while the CPU resumes its data processing functions. In conjunction with the indirect addressing scheme, the MPAC circuit also employs a memory buffering technique that substantially reduces the amount of system memory that need be dedicated for use by the MPAC circuit.
However, merely designing a circuit to perform a function is not sufficient to ensure that it will be economical to manufacture the circuit as a MOS LSI chip. The primary consideration in the economical manufacture of MOS LSI circuits is minimizing the amount of substrate material (such as silicon) required to produce an integrated circuit chip, thus allowing a greater chip yield per substrate wafer.
The surface geometry of the MOS circuitry is formed on a chip and the interconnection pattern of conductors therebetween must be optimized to provide the highest functional component density in order to reduce overall chip area per circuit function. Minimum geometry spacings between metallization lines, diffused regions, and polycrystalline silicon conductors must be maintained, yet the length of such lines and their associated capacitances must be minimized in order to optimize circuit performance as the complex interconnection patterns are implemented. Parasitic electrical effects on the circuitry also must be minimized or compensated for in the chip layout. A very high degree of creativeness is thus required of the chip architect in order to choose a particular layout and interconnection pattern for an LSI circuit from the very large number of possibilities that exist for arranging such a circuit. Frequently, the commercial success of a MOS LSI product may hinge on the ability of a chip architect to achieve an optimum chip topography.
By creatively structuring the topographic layout of the MPAC chip, the present invention allows a MOS LSI chip size of 266 mils by 263 mils, with a processing speed of up to 1.6 megabits per second, or even more. The preferred embodiment of the present invention is fabricated in N-channel, self-aligned silicon gate MOS technology, and is TTL compatible on all inputs and outputs.
It is therefore an object of this invention to provide a packet network interface circuit having a novel data addressing and memory buffering scheme that substantially improves the performance of a data communications system using the circuit.
It is another object of this invention to provide an optimum semiconductor chip topography for a MOS LSI chip implementation of the standards specified in CCITT Recommendation X.25.
It is a further object of this invention to provide an optimum chip topography for a MOS LSI packet network interface circuit.
It is yet a further object of this invention to provide a bonding pad sequence for a MOS LSI MPAC chip selected to allow optimum arrangement of packages containing the MPAC chip on a printed circuit board.